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Автор Сообщение
 Заголовок сообщения: MPC8308 DMA
СообщениеДобавлено: 25 апр 2019, 10:16 
Здравствуйте!

Зарегистрирован: 25 апр 2019, 10:09
Сообщения: 1
Доброго времени суток.
Столкнулся с задачей требующей использования DMA на MPC8308.
Но так и не получилось.
Сделал вот так.

Код:
#define CONFIG_SYS_IMMR      0xE0000000  ///it is address IMMR. This address is set by U-Boot. Unfortunately idk how i can find it in a dynamic.
//ENHANCED_LOCAL_BUS_CONTROLLER_BLOCK_BASE_ADDRESS
enum Base_Addresses
{
   ENHANCED_LOCAL_BUS_CONTROLLER_BLOCK_BASE_ADDRESS = 0x5000
};

enum eLBC_map
{
   BR0 = 0x0,
   OR0 = 0x4,
   BR1 = 0x8,
   OR1 = 0xC,
   BR2 = 0x10,
   OR2 = 0x14,
   BR3 = 0x18,
   OR3 = 0x1C,
   MAR = 0x68,
   MAMR = 0x70,
   MBMR = 0x74,
   MCMR = 0x78,
   MRTPR = 0x84,
   MDR = 0x88,
   LSOR = 0x90,
   LURT = 0xA0,
   LTESR = 0xB0,
   LTEDR = 0xB4,
   LTEIR = 0xB8,
   LTEATR = 0xBC,
   LTEAR  = 0xC0,
   LTECCR = 0xC4,
   LBCR = 0xD0,
   LCRR = 0xD4,
   FMR = 0xE0,
   FIR = 0xE4,
   FCR = 0xE8,
   FBAR = 0xEC,
   FPAR = 0xF0,
   FBCR = 0xF4,
   FECC0 = 0x100,
   FECC1 = 0x104,
   FECC2 = 0x108,
   FECC3 = 0x10C
};


enum AM_vals
{
   Sz_4_Gbytes =   (0x1FFFF >> 17)<<17,
   Sz_2_Gbytes =   (0x1FFFF >> 16)<<16,
   Sz_1_Gbytes =   (0x1FFFF >> 15)<<15,
   Sz_512_Mbytes = (0x1FFFF >> 14)<<14,
   Sz_256_Mbytes = (0x1FFFF >> 13)<<13,
   Sz_128_Mbytes = (0x1FFFF >> 12)<<12,
   Sz_64_Mbytes =  (0x1FFFF >> 11)<<11,
   Sz_32_Mbytes =  (0x1FFFF >> 10)<<10,
   Sz_16_Mbytes =  (0x1FFFF >> 9)<<9,
   Sz_8_Mbytes =   (0x1FFFF >> 8)<<8,
   Sz_4_Mbytes =   (0x1FFFF >> 7)<<7,
   Sz_2_Mbytes =   (0x1FFFF >> 6)<<6,
   Sz_1_Mbytes =   (0x1FFFF >> 5)<<5,
   Sz_512_Kbytes = (0x1FFFF >> 4)<<4,
   Sz_256_Kbytes = (0x1FFFF >> 3)<<3,
   Sz_128_Kbytes = (0xFFFFF >> 2)<<2
};


enum SCY_cycles_lenght_in_bus_clock_vals
{
   NoWaits = 0,
   bus_clock_cycle_wait_state_1  = 1,
   bus_clock_cycle_wait_state_2  = 2,
   bus_clock_cycle_wait_state_3  = 3,
   bus_clock_cycle_wait_state_4  = 4,
   bus_clock_cycle_wait_state_5  = 5,
   bus_clock_cycle_wait_state_6  = 6,
   bus_clock_cycle_wait_state_7  = 7,
   bus_clock_cycle_wait_state_8  = 8,
   bus_clock_cycle_wait_state_9  = 9,
   bus_clock_cycle_wait_state_10 = 10,
   bus_clock_cycle_wait_state_11 = 11,
   bus_clock_cycle_wait_state_12 = 12,
   bus_clock_cycle_wait_state_13 = 13,
   bus_clock_cycle_wait_state_14 = 14,
   bus_clock_cycle_wait_state_15 = 15,

};


enum ETHR_vals
{
   No_Additional_cycles_are_inserted = 0,
   idle_clock_cycle_is_inserted_1    = 1,
   idle_clock_cycle_is_inserted_4    = 2,
   idle_clock_cycle_is_inserted_8    = 3,
};

#pragma pack(1)
struct ORn_GPCM_Mode
{
   unsigned Reserved2 : 1;//always 0
   unsigned EHTR      : 1;//ETHR_vals
   unsigned TRLX      : 1;///1 or 0
   unsigned SETA      : 1;//1 or 0
   unsigned SCY       : 4;//SCY_cycles_lenght_in_bus_clock_vals
   unsigned XACS      : 1;//1 or 0
   unsigned ACS       : 2;//
   unsigned CSNT      : 1;
   unsigned BCTLD     : 1;
   unsigned Reserved1 : 2;
   unsigned AM        : 17;//AM_vals
};




struct DMACR_str
{
   unsigned   Reserved : 14;
   unsigned         CX : 1;//0 Normal operation.
                     //1 Cancel the remaining data transfer
   unsigned        ECX : 1;//0 Normal operation.
                     //1 Cancel the remaining data transfer in the same fashion as the CX cancel transfer.
   unsigned  Reserved2 : 8;
   unsigned       EMLM : 1;//0 Minor loop mapping disabled. TCDn.word2 is defined as a 32-bit nbytes field.
                     //1 Minor loop mapping enabled
   unsigned        CLM : 1;//0 A minor loop channel link made to itself will go through channel arbitration before being activated again.
                     //1 A minor loop channel link made to itself will not go through channel arbitration before being activated again.
   unsigned       HALT : 1;//Halt on error.
                    //0 Normal operation.
                    //1 Any error causes the HALT bit to be set. Subsequently, all service requests will be ignored until the HALT bit is cleared.
   unsigned        HOE : 1; //Halt on error.
                      //0 Normal operation.
                      //1 Any error causes the HALT bit to be set. Subsequently, all service requests will be ignored until the HALT bit is cleared.
   unsigned  Reserved3 : 1;
   unsigned       ERCA : 1;//Enable round robin channel arbitration.
                     //0 Fixed priority arbitration is used for channel selection.
                     //1 Round robin arbitration is used for channel selection.
   unsigned        EDBG : 1;//Enable debug.
                      //0 The assertion of the ipg_debug input is ignored.
                      //1 The assertion of the ipg_debug input causes the DMA to stall the start of a new channel.
   unsigned         EBW : 1;//Enable buffered writes.
                      //0 The bufferable write signal (hprot[2]) is not asserted during AHB writes.
                      //1 The bufferable write signal (hprot[2]) is asserted on all AHB writes except for the last write sequence write sequence.
};

struct DMAES_str
{
   unsigned         VLD : 1;//Logical OR of all the DMAERR status bits.
                       //0 No DMAERR bits are set.
                      //1 At least one DMAERR bit is set indicating a valid error exists that has not been cleared.
   unsigned    Reserved : 14;
   unsigned         ECX : 1;//Transfer cancelled.
                    //0 No cancelled transfers
                    //1 The last recorded entry was a cancelled transfer via the error cancel transfer input.
   unsigned   Reserved2 : 1;
   unsigned         CPE : 1;//Channel priority error.
                    //0 No channel priority error.
                    //1 The last recorded error was a configuration error in the channel priorities. All channel priorities are not unique.
   unsigned      ERRCHN : 6;//Error channel number or cancelled channel number. The channel number of the last recorded error (excluding CPE errors) or last recorded transfer that was error cancelled.
   unsigned         SAE : 1;//Source address error.
                    //0 No source address configuration error.
                    //1 The last recorded error was a configuration error detected in the TCD.saddr field. TCD.saddr is inconsistent with TCD.ssize.
   unsigned         SOE : 1;//Source offset error.
                    //0 No source offset configuration error.
                    //1 The last recorded error was a configuration error detected in the TCD.soff field. TCD.soff is inconsistent with TCD.ssize.
   unsigned         DAE : 1;//Destination address error.
                    //0 No destination address configuration error.
                    //1 The last recorded error was a configuration error detected in the TCD.daddr field. TCD.daddr is inconsistent with TCD.dsize.
   unsigned         DOE : 1;//Destination offset error.
                    //0 No destination offset configuration error.
                    //1 The last recorded error was a configuration error detected in the TCD.doff field. TCD.doff is inconsistent with TCD.dsize
   unsigned         NCE : 1;//Nbytes/citer configuration error.
                    //0 No nbytes/citer configuration error.
                    //1 The last recorded error was a configuration error detected in the TCD.nbytes or TCD.citer fields.
                    //TCD.nbytes is not a multiple of TCD.ssize and TCD.dsize, or TCD.citer is equal to zero, or TCD.citer.e_link is not equal to TCD.biter.e_link.
   unsigned         SGE : 1;//Scatter/gather configuration error.
                    //0 No scatter/gather configuration error.
                    //1 The last recorded error was a configuration error detected in the TCD.dlast_sga field. This field is
                    //checked at the beginning of a scatter/gather operation after major loop completion if TCD.e_sg is enabled. TCD.dlast_sga is not on a 32 byte boundary.
   unsigned         SBE : 1;//Source bus error.
                    //0 No source bus error.
                    //1 The last recorded error was a bus error on a source read.
   unsigned         DBE : 1;//Destination bus error.
                    //0 No destination bus error.
                    //1 The last recorded error was a bus error on a destination write.
};

struct DMAEEI_str
{
   unsigned Reserved : 16;
   unsigned EEI15 : 1;//Enable error interrupt n.
               //0 The error signal for channel n does not generate an error interrupt.
               //1 The assertion of the error signal for channel n generate an error interrupt request.
   unsigned EEI14 : 1;
   unsigned EEI13 : 1;
   unsigned EEI12 : 1;
   unsigned EEI11 : 1;
   unsigned EEI10 : 1;
   unsigned EEI9  : 1;
   unsigned EEI8  : 1;
   unsigned EEI7  : 1;
   unsigned EEI6  : 1;
   unsigned EEI5  : 1;
   unsigned EEI4  : 1;
   unsigned EEI3  : 1;
   unsigned EEI2  : 1;
   unsigned EEI1  : 1;
   unsigned EEI0  : 1;
};

struct DMASEEI_str
{
   unsigned NOP  : 1;//No operation.
               //0 Normal operation.
                //1 No operation, ignore bits 6–0.
   unsigned SEEI : 7;//Set enable error interrupt.
               //0–15 Set the corresponding bit in DMAEEI.
               //16–63 Reserved
               //64–127 Set all bits in DMAEEI.
};

struct DMACEEI_str
{
   unsigned NOP  : 1;//No operation.
               //0 Normal operation.
               //1 No operation, ignore bits 6–0.
   unsigned CEEI : 7;//Clear enable error interrupt.
               //0–15 Clear corresponding bit in DMAEEI.
                   //16–63 Reserved
                   //64–127 Clear all bits in DMAEEI.
};

struct DMACINT_str
{
   unsigned NOP  : 1;//No operation.
               //0 Normal operation.
               //1 No operation, ignore bits 6–0.
   unsigned CINT : 7;//Clear interrupt request.
               //0–15 Clear the corresponding bit in DMAINT.
               //16–63 Reserved
               //64–127 Clear all bits in DMAINT.
};

struct DMACERR_str
{
   unsigned NOP  : 1;//No operation.
               //0 Normal operation.
               //1 No operation, ignore bits 6–0.
   unsigned CERR : 7;//Clear error indicator.
               //0–15 Clear corresponding bit in DMAERR.
                   //16–63 Reserved
                   //64–127 Clear all bits in DMAERR.
};

struct DMASSRT_str
{
   unsigned NOP  : 1;//No operation.
               //0 Normal operation.
               //1 No operation, ignore bits 6–0.
   unsigned SSRT : 7;//Set START bit (channel service request).
               //0–15 Set the corresponding channel’s TCD.start.
                   //16–63 Reserved
               //64–127 Set all TCD.start bits.
};

struct DMACDNE_str
{
   unsigned NOP  : 1;//No operation.
               //0 Normal operation.
               //1 No operation, ignore bits 6–0.
   unsigned CDNE : 7;//Clear DONE status bit.
               //0–15 Clear the corresponding channel’s DONE bit.
               //16–63 Reserved
                  //64–127 Clear all TCD DONE bits.
};

struct DMAINT_str
{
   unsigned Reserved : 16;
   unsigned INT15 : 1;//DMA interrupt request n (write one to clear)
               //0 The interrupt request for channel n is cleared.
               //1 The interrupt request for channel n is active.
   unsigned INT14 : 1;
   unsigned INT13 : 1;
   unsigned INT12 : 1;
   unsigned INT11 : 1;
   unsigned INT10 : 1;
   unsigned INT9  : 1;
   unsigned INT8  : 1;
   unsigned INT7  : 1;
   unsigned INT6  : 1;
   unsigned INT5  : 1;
   unsigned INT4  : 1;
   unsigned INT3  : 1;
   unsigned INT2  : 1;
   unsigned INT1  : 1;
   unsigned INT0  : 1;
};


struct DMAERR_str
{
   unsigned Reserved : 16;
   unsigned ERR15 : 1;//DMA error n (write one to clear)
                //0 An error in channel n has not occurred.
               //1 An error in channel n has occurred.
   unsigned ERR14 : 1;
   unsigned ERR13 : 1;
   unsigned ERR12 : 1;
   unsigned ERR11 : 1;
   unsigned ERR10 : 1;
   unsigned ERR9  : 1;
   unsigned ERR8  : 1;
   unsigned ERR7  : 1;
   unsigned ERR6  : 1;
   unsigned ERR5  : 1;
   unsigned ERR4  : 1;
   unsigned ERR3  : 1;
   unsigned ERR2  : 1;
   unsigned ERR1  : 1;
   unsigned ERR0  : 1;
};


struct DMAGROP_str
{
   unsigned Reserved       : 19;
   unsigned DMA_PRIORITY   : 1;//DMA priority.
                       //0 Low priority
                       //1 High priority
   unsigned Reserved2      : 5;
   unsigned SNOOP_ENABLE   : 1;//Snoop attribute.
                       //0 DMA transactions are not snooped by e300 CPU data cache
                       //1 DMA transactions are snooped by e300 CPU data cache
   unsigned Reserved3      : 1;
   unsigned ERROR_DISABLE  : 1;//Ignore or react to bus errors.
                       //0 React to bus transaction errors
                      //1 Ignore bus transaction errors
   unsigned Reserved4      : 1;
   unsigned RD_SAFE_ENABLE : 1;//Read Safe enable. This bit should be set only if the target of read dma operation is a well
                      //behaved memory which is not affected by the read operation and returns the same data if read
                      //again from the same location. This means that unaligned reading operation can be rounded up
                      //to enable more efficient read operations.
                      //0 It is not safe to read more bytes that were intended
                      //1 It is safe to read more bytes that were intended
   unsigned Reserved5 : 1;
};


struct DCHPR_str
{
   unsigned ECP      : 1;//Enable channel preemption.
                   //0 Channel n cannot be suspended by a higher priority channel’s service request.
                   //1 Channel n can be temporarily suspended by the service request of a higher priority channel.
   unsigned DPA      : 1;//Disable preempt ability.
                   //0 Channel n can suspend a lower priority channel.
                    //1 Channel n cannot suspend any channel, regardless of channel priority.
   unsigned Reserved : 2;
   unsigned CHPRI    : 4;//Channel n arbitration priority. Channel priority when fixed-priority arbitration is enabled.
};


#define DMAC_str_Offset 0x2C000

struct DMAC_str
{
   DMACR_str DMACR;
   DMAES_str DMAES;
   uint8_t Reserved1[0xC];
   DMAEEI_str DMAEEI;
   uint8_t Reserved2[0x2];
   DMASEEI_str DMASEEI;
   DMACEEI_str DMACEEI;
   DMACINT_str DMACINT;
   DMACERR_str DMACERR;
   DMASSRT_str DMASSRT;
   DMACDNE_str DMACDNE;
   uint8_t Reserved3[0x4];
   DMAINT_str DMAINT;
   uint8_t Reserved4[0x4];
   DMAERR_str DMAERR;
   uint8_t Reserved5[0x8];
   DMAGROP_str DMAGROP;
   uint8_t Reserved6[0xC4];
   DCHPR_str DCHPR[16];SPP_DMA2_TCDWORD0__32B_tag
   uint8_t Reserved7[0xEBC];
};


struct tcd_attr
{
   unsigned smod  : 5;//Source address modulo.
   unsigned ssize : 3;//Source data transfer size.
                  //000 8-bit
                  //001 16-bit
                   //010 32-bit
                  //011 64-bit
                  //100 16-byte
                  //100 Reserved
                  //101 32-byte
                  //110 Reserved
                  //111 Reserved
   unsigned dmod  : 5;//Destination address modulo.
   unsigned dsize : 3;//Destination data transfer size.
                  //000 8-bit
                  //001 16-bit
                   //010 32-bit
                  //011 64-bit
                  //100 16-byte
                  //100 Reserved
                  //101 32-byte
                  //110 Reserved
                  //111 Reserved
};

struct tcd_citer
{
   unsigned  e_link : 1;//0 The channel-to-channel linking is disabled.
                   //1 The channel-to-channel linking is enabled.
   unsigned  citer  : 15;//Current major iteration count or link channel number.
};

struct tcd_biter
{
   unsigned  e_link : 1;//0 The channel-to-channel linking is disabled.
                   //1 The channel-to-channel linking is enabled.
   unsigned  biter  : 15;//Beginning major iteration count or beginning link channel number
};

struct tcd_ccr
{
   unsigned biter : 9;//Beginning major iteration count;
   unsigned bwc : 2;//Bandwidth
   unsigned major_linkch : 6;//Link channel number;
   unsigned done : 1;//Channel done
   unsigned active : 1;//Channel active;
   unsigned major_e_link : 1;//Enable channel-to-channel linking on major loop complete;
   unsigned e_sg;//Enable scatter/gather processing;
   unsigned Reserved : 1;
   unsigned int_half : 1;//Enable an interrupt when major counter is half complete;
   unsigned int_maj : 1;//Enable an interrupt when major iteration count completes;
   unsigned start : 1;//Channel start;

};




/* TCD - eDMA*/
typedef struct tcd_ctrl {
   uint32_t saddr;      /* 0x00 Source Address */
   tcd_attr attr;   /* 0x04 Transfer Attributes */
   uint16_t soff;      /* 0x06 Signed Source Address Offset */
   uint32_t nbytes;      /* 0x08 Inner Minor Byte Count */
   uint32_t slast;      /* 0x0C Last Source Address Adjustment */
   uint32_t daddr;      /* 0x10 Destination address */
   tcd_citer citer;   /* 0x14 Cur Minor Loop Link, Major Loop Cnt */
   uint16_t doff;      /* 0x16 Signed Destination Address Offset */
   uint32_t dlast_sga;   /* 0x18 Last Dest Adr Adj/Scatter Gather Adr */
   tcd_biter biter;      /* 0x1C Minor Loop Lnk, Major Loop Cnt */
   tcd_ccr ccr;      /* 0x1E Control and Status */
} tcd_st;


#pragma pack()

#define DMA_Offset_TCD 0x1000
static volatile DMAC_str *DMAC;
static volatile tcd_ctrl *TCD_;



hCPLD      = open("/dev/mem", O_RDWR | O_SYNC);
DMAC = (DMAC_str *)mmap(0, 0x001000, PROT_READ  , MAP_SHARED, hCPLD, CONFIG_SYS_IMMR + DMAC_str_Offset);
TCD_ = (tcd_ctrl *)mmap(0, 0x001000, PROT_READ   | PROT_WRITE, MAP_SHARED, hCPLD, CONFIG_SYS_IMMR + DMAC_str_Offset + 0x1000);
volatile char* Dest = new char[1024];
for(int i = 0; i < 1024; i++)Dest[i] = 0x1;
TCD_->daddr = (uint32_t)Dest;
TCD_->nbytes = 16;
TCD_->citer.citer = TCD_->biter.biter = 1;
TCD_->soff = 1;
TCD_->attr.ssize = 0;
TCD_->slast = 0;
TCD_->saddr = (uint32_t)0xF0000000;
TCD_->doff = 4;
TCD_->attr.dsize = 2;
TCD_->dlast_sga = -16;
TCD_->ccr.int_maj = 1;
TCD_->ccr.start = 1;
__asm__ __volatile__ ("sync");
__asm__ __volatile__ ("isync");



Но то ли, структуры не правильные, то ли сама идеология не верна.
Если у кого есть опыт с DMA на MPC8308 буду признателен за подсказки.


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